The steps involved in a typical design of an integrated circuit include 1) circuit design, 2) layout design, 3) design-rule checking, 4) creating pattern-generation files, 5) mask making, 6) fabrication, 7) packaging, and 8) testing. The present invention relates to the creation of pattern-generation files.
The process of making an integrated circuit starts with a circuit design of a desired function. The circuit design is typically simulated to guarantee proper operation. After the circuit design has been finalized, the physical layout of the circuit design is initiated. The physical layout is a series of polygons placed on various processing layers in such a way that fabrication of all of the polygons from all of the layers yields the intended circuit design.
There are two variables associated with a physical layout. One variable is the process. For example, the circuit design may have been designed for a double-metal, twin-well, Complementary Metal Oxide Semiconductor (CMOS) process. That is a process having an n-well layer, a p-well layer, an active area layer, a polysilicon layer, a p+ diffusion layer, an n+ diffusion layer, a first contact layer, a first metal layer, a second contact layer, a second metal layer, and a passivation layer.
Polygons created on the n-well layer define openings in silicon-dioxide through which n-type material can be diffused into the semiconductor substrate. P-channel transistors can subsequently be formed in the n-wells. Polygons created on the p-well layer define openings in silicon-dioxide through which p-type material can be diffused into the semiconductor substrate. N-channel transistors can subsequently be formed in the p-wells. Polygons created on the active area layer define openings in silicon-dioxide through which either n-type or p-type material can be diffused into the n-well or p-well. The source and drain of a p-channel transistor are simultaneously formed when p-type material is diffused through an active area polygon which is placed over and within an n-well polygon. The source and drain of an n-channel transistor are simultaneously formed when n-type material is diffused through an active area polygon over and within a p-well polygon. For a self-aligned silicon-gate process, a polygon on the polysilicon layer is created over a p-well (or an n-well) and under an active area so that. a polysilicon gate is formed between the source and drain of an n-channel (or p-channel) transistor.
Polygons on the polysilicon layer define where silicon will be deposited. onto the semiconductor wafer. Since the deposited silicon contains silicon crystals of various orientations, the deposited silicon is referred to as poly-crystalline silicon or polysilicon for short. The polysilicon deposited over an active area forms a gate between the drain and source of an n-channel (or p-channel) transistor. The polysilicon deposited outside of an active area acts as interconnect to other transistor gates or to other layers if a proper inter-layer structure is employed.
Polygons created on the first-contact layer define inter-layer structures between the polysilicon layer and the first-metal layer. Polygons on the first-contact layer are openings in silicon-dioxide through which metal can be deposited. Polygons on the first-metal layer define openings in the silicon-dioxide through which metal interconnect structures can be formed. A typical polysilicon-to-first-metal structure would consist of a polysilicon interconnect structure having one end under one end of a first-metal interconnect structure where the first-contact would be between these two ends. When metal is deposited for the first-metal interconnect structure, metal will also be deposited on the polysilicon interconnect structure via the first-contact layer so that the two interconnect layers are electrically connected.
Polygons created on the second-contact layer define inter-layer structures between the first-metal layer and the second-metal metal layer. Polygons on the second-contact layer are openings in silicon-dioxide through which metal can be deposited. Polygons on the second-metal layer define openings in the silicon-dioxide through which metal interconnect structure can be formed. A typical first-metal-to-second-metal structure would consist of a first-metal interconnect structure having one end under one end of a second-metal interconnect structure where the second-contact would be between these two ends. When metal is deposited for the second-metal interconnect structure, metal will also be deposited on the first-metal interconnect structure via the second-contact polygon so that the two interconnect layers are electrically connected.
Polygons created on the passivation layer are openings in the silicon-dioxide over the bond pads through which bondwires are connected.
The second variable in the layout of a circuit design is the technology (i.e., the minimum gate width of a transistor). Presently, technologies are at 1.25 microns, 1.0 microns, and 0.8 microns. A technology-independent layout design can be scaled to accommodate various technologies.
After the layout is completed, the layout is typically checked to ensure that it adheres to the rules associated with a particular vendor at which the semiconductor wafers will be fabricated. Before fabrication can start, the layout information (i.e., the polygons on the various layers) must be converted to a pattern-generation file. The pattern-generation file is used to create a mask for each of the layers in the semiconductor process (e.g., twin-well, double-metal CMOS). Each mask may contain all of the information needed to expose an entire semiconductor wafer (i.e., full wafer lithography) or each mask may contain a portion of the information needed to expose a portion of the semiconductor wafer (i.e., reticle-based lithography). In reticle-based lithography, a portion of a semiconductor wafer is exposed to the reticle. The wafer is then stepped so that another portion of the wafer can be exposed to the reticle. This procedure is repeated until the entire wafer has been exposed to the reticle.
The masks may contain one copy of a particular layout design, multiple copies of a particular layout design, or multiple copies of numerous layout designs. If multiple copies of a particular layout design or multiple copies of numerous layout designs are contained on one mask, each layout design is separated from the adjacent layout design by a scribe line (i.e., a line in which no circuitry is placed).
The present invention allows a user to input technology-independent and process-independent layout designs, define the technology and the process, create the desired mask placement of at least one layout design using full-wafer and reticle-based lithography, add scribe lines manually and automatically, and convert the resulting information into a MEBES pattern-generation file that can subsequently be used to manufacture integrated-circuit masks. The present invention is an improvement upon a method used by the University of Southern California (USC) in connection with its Metal Oxide Semiconductor Implementation Service (MOSIS). The inventors believe that the present invention does in one day what it takes the USC method three days to complete. The present invention allows for easy entry of technology and process selection where the USC method does not. The present invention is believed to have an improved graphical interface as compared to the USC method. The USC method requires the use of a Digital Equipment Corporation VMS operating system where the present invention does not. The present invention can automatically generate scribe lines where the USC method can not. The present invention provides status information that the USC method does not. The present invention allows layout designs to be input automatically where the USC method does not.
U.S. Pat. No. 5,161,114, entitled "METHOD OF MANUFACTURING A RETICLE," discloses a method of combining design data with alignment mark data.
U.S. Pat. No. 4,849,313, entitled "METHOD FOR MAKING A RETICLE MASK," discloses a method of placing alignment marking in the scribe lines so that die patterns can be placed in the reticle in relation to these alignment marks.
U.S. Pat. No. 4,610,940, entitled "METHOD FOR FABRICATING A PHOTOMASK PATTERN," discloses a method of using vernier patterns to measure printing shear. The present invention differs from the prior art in that the present invention pertains to a new method of converting layout design information into a pattern-generation file that can be used to create integrated-circuit masks, and more particularly to a method of converting layout design information into a MEBES pattern-generation file. MEBES files are used in conjunction with electron-beam lithography techniques. Electron-beam lithography is more precise than optical lithography.
U.S. Pat. No. 5,212,653, entitled "METHOD FOR PRODUCING A LAYOUT OF ELEMENT PORTIONS FOR A SEMICONDUCTOR INTEGRATED CIRCUIT USING A COMPUTER," discloses a method of using a computer to automatically generate a compact layout of a single bipolar integrated-circuit design. The present invention starts where U.S. Pat. No. 5,212,653 leaves off by disclosing a method of using a computer for arranging multiple copies of one or more integrated-circuit design, for which layout has already been completed, to form a computer tape containing the information necessary to create fabrication masks.
U.S. Pat. No. 5,164,907, entitled "COMPUTER AIDED DESIGN SYSTEM CAPABLE OF PLACING FUNCTIONAL BLOCKS WITH A CIRCUIT CONSTRAINT SATISFIED," discloses a method of using a computer to automatically generate a compact layout of a single integrated-circuit design. Again, the present invention does not deal with producing the layout of an integrated circuit but deals with the arrangement of integrated circuits, for which layout is complete, in order to produce a computer tape that can be used to make MEBES fabrication masks. The same can be said for U.S. Pat. No. 4,831,546, entitled "METHOD AND APPARATUS FOR ASSISTING LAYOUT DESIGN."
U.S. Pat. No. 4,869,998, entitled "INTEGRATED CIRCUIT SUBSTRATES," discloses a method of exposing integrated-circuit substrates to a composite representation in a regular and repeating manner. The present invention discloses a method of using a computer to create a computer tape of a single representation of one or more integrated-circuit designs that will be used to create fabrication masks that will be exposed once to a semiconductor wafer or a computer tape of a composite representation that will be used to create fabrication masks that will be exposed a number of times to a semiconductor wafer.